Hugepages — why and how

The TLB Bottleneck

Every memory access on a CPU goes through the Translation Lookaside Buffer (TLB) — a small cache mapping virtual addresses to physical addresses. The TLB has typically 64-512 entries depending on the CPU and access type. With standard 4 KB pages, a 64 MB working set (typical for a DPDK packet buffer pool) requires 16,384 distinct page table entries — vastly more than the TLB can hold. Every access risks a TLB miss, which costs a page-table walk (often 4 memory references to traverse the page table levels). At line-rate packet processing this is catastrophic. With 2 MB hugepages the same 64 MB…